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te ch tm preliminary t4312816a tm technology inc. reserves the right p. 1 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b sdram 8m x 16 sdram 2m x 16bit x 4banks synchronous dram features ? 3.3v power supply ? four banks operation ? lvttl compatible with multiplexed address ? all inputs are sampled at the positive going edge of system clock ? burst read single-bit write operation ? dqm for masking ? auto refresh and self refresh ? 64ms refresh period (4k cycle) ? mrs cycle with address key programs - cas latency ( 2 & 3 ) - burst length ( 1 , 2 , 4 , 8 & full page) - burst type (sequential & interleave) ? available package type in 54 pin tsop(ii) ? operating temperature : 0 ~ +70 c ordering information grneral description the t4312816a is 134,217,728 bits synchronous high data rate dynamic ram organized as 4 x 2,097,152 words by 16 bits, fabricated with high performance cmos technology . synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clockcycle . range of operating frequencies , programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications. pin arrangement ( top view) dq1 v dd 46 45 44 43 41 42 40 36 35 34 33 32 31 30 29 1 2 3 4 6 5 7 8 9 11 15 16 17 18 19 20 v ddq dq11 dq1 0 a8 a7 a9 10 21 22 47 48 49 50 v ssq dq2 a0 a1 dq15 dq14 vss 23 24 25 28 27 26 dq3 dq0 v ddq dq4 dq5 v ssq dq6 ras cs ba1 a10/a p a2 a3 v dd v ssq dq13 dq12 dq9 udqm n.c clk cke vss a6 a5 a4 12 13 14 39 38 37 dq7 v dd ld qm dq8 vss n.c/rfu w e cas 5 4 p in t s o p (ii) (400m il x 875m il) (0.8 mm pin pitch) 51 52 53 54 v ddq ba0 v ddq v ssq a11 part no. max frequency temperature t4312816a-6s 166 mhz 0 ~ +70 c t4312816a-7s 143 mhz 0 ~ +70 c t4312816a-7.5s 133 mhz 0 ~ +70 c t4312816a-8s 125 mhz 0 ~ +70 c t4312816a-10s 100 mhz 0 ~ +70 c
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 2 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b block diagram data input register i/o control output buffer 2m x 16 2m x 16 sense amp column decoder latency & burst length programming register bank select row buffeer refresh counter row decoder address register col. buffer timing register dqi l(u)dqm ras cs cke clk lcbr lras add clk cas we 2m x 16 2m x 16
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 3 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b pin description pin name input function clk system clock active on the positive going edge to sample all input. cs chip select disables or enables device operation by masking or enabling all input except clk,cke and l(u)dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a11 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra11,column address : ca0 ~ ca8 ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. select bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access . we write enable enables write operation and row precharge. latches data in starting from cas , we active. l(u)dqm data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when l(u)dqm active. dq0 ~ dq15 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity. n.c/rfu no connection/reserved for future use this pin is recommended to be left no connection on the device.
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 4 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0 to 4.6 v supply voltage relative to vss v dd ,v ddq -1.0 to 4.6 v short circuit output current i out 50 ma power dissipation p d 1 w operating temperature t opr 0 to +70 c storage temperature t stg -55 to +150 c note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions (t a = 0 to +70 c , voltage referenced to v ss =0v) parameter symbol min. typ max. unit notes supply voltage v dd ,v ddq 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v dd +0.3v v input low voltage v il -0.3 0 0.8 v output logic high voltage v oh 2.4 - - v i oh =-4ma output logic low voltage v ol - - 0.4 v i ol =4ma input leakage current i il -1 - 1 ua 1 output leakage current i ol -1.5 - 1.5 ua 2 note : 1. any input 0v v in v dd + 0.3v , all other pin are not under test = 0v. 2. dout = disable, 0v v out v dd . capacitance (t a =25 c ,v dd =3.3v, f = 1mhz) pin symbol min max unit clock c clk 2.5 4.0 pf address c add 2.5 5.0 pf dq0 ~ dq15 c out 4.0 6.5 pf ras,cas,we,cs,cke,ldqm, udqm c in 2.5 5.0 pf
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 5 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b dc characteristics t a = 0 to 70 c , v ih (min)/v il (max)=2.0v/0.8v speed version parameter symbol -6 -7 -7.5 -8 -10 unit test condition note operating current ( one bank active) i cc1 140 120 115 110 100 ma burst length = 1 t rc t rc (min) , t cc t cc (min),i ol = 0 ma 1,3 i cc2 p 2 cke v il (max), t cc =15ns precharge standby current in power- down mode i cc2 ps 2 ma cke v il (max),clk v il (max), t cc = 3 i cc2 n 20 cke v ih (min), cs v ih (min), t cc =15ns input signals are changed one time during 30ns precharge standby current in non power-down mode i cc2 ns 8 ma cke v ih (min),clk v il (min), t cc = input signals are stable 3 i cc3 p 5 cke vil(max), t cc =15ns active standby current in power- down mode i cc3 ps 4 ma cke v il (max),clk v il (max), t cc = 3 i cc3 n 30 cke v ih (min), cs v ih (min), t cc =15ns input signals are changed one time during 30ns active standby current in non power-down mode (one bank active) i cc3 ns 20 ma cke v ih (min),clk v il (min), t cc = input signals are stable 3 150 130 125 120 110 cas latency 3 operating current (burst mode) i cc4 150 130 125 120 110 ma cas latency 2 i ol =0 ma,page burst all band activated t ccd = t ccd (min) 1,3 refresh current i cc5 150 130 125 120 110 ma t rc t rc (min) 2,3 self refresh current i cc6 2 ma cke 0.2v note: 1. measured with output open. addresses are changed only one time during t cc (min) . 2. refresh period is 64ms. addresses are changed only one time during t cc (min) . 3. t cc : clock cycle time. t rc : row cycle time. t ccd : column address to column address delay time.
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 6 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b ac operating conditions (v dd =3.3v 0.3v ,t a = 0 to 70 c ) parameter value unit input levels (v ih /v il ) 2.4 / 0.4 v input timing measurement reference level 1.4 v input rise and fall time t r / t f = 1 / 1 ns output timing measurement reference level 1.4 v output load condition see fig.2 3.3v 1200 ohm output 870 ohm 30pf voh(dc)=2.4,ioh=-4ma vol(dc)=0.4,iol=4ma zo=50 ohm output 50 ohm vtt=1.4v 30pf (fig.1) dc output load circuit (fig.2)ac output load circuit
te ch tm preliminary t4312816a tm technology inc. reserves the right p. 7 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b operating ac parameter (ac opterating conditions unless otherwise noted) speed version parameter symbol -6 -7 -7.5 -8 -10 unit note row active to row active delay t rrd (min) 12 14 15 16 20 ns 1 ras to cas delay t rcd (min) 15 15 18 20 20 ns 1 row precharge time t rp (min) 15 15 20 20 20 ns 1 t ras (min) 42 42 45 48 50 ns 1 row active time t ras (max) 120k ns row cycle time t rc (min) 60 63 65 68 70 ns 1 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to row precharge t rdl (min) 2 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 cas latency=3 1 number of valid output data cas latency=2 1 ea 4 note: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. the earliest a precharge command can be issued after a read command without the loss of data is cl + bl-2 clocks.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.8 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b ac characteristics (ac opterating conditions unless otherwise noted) -6 -7 -7.5 -8 -10 parameter symbol min max min max min max min max min max unit note cas latency = 3 6 1k 7 1k 7.5 1k 8 1k 10 1k clk cycle time cas latency = 2 t cc 8 9 9 10 10 ns 1 cas latency = 3 - 5.5 - 6 6 - 6 - 7 ns clk to valid output delay cas latency = 2 t sac - 6 - 6 6 - 7 - 9 ns 1 output data hold time t oh 2 2.5 2.5 2.5 2.5 ns 2 clk high pulse width t ch 2 2.5 2.5 3 3 ns 3 clk low pulse width t cl 2 2.5 2.5 3 3 ns 3 input setup time t ss 1.5 1.75 1.75 2 2.5 ns 3 input hold time t sh 1 1 1 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 1 ns 2 cas latency = 3 - 5.5 - 6 6 - 6 - 7 ns clk to output in hi-z cas latency = 2 t shz - 6 - 6 6 - 7 - 9 ns note: 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns,transient time compensation should be considered, i.e.,[(tr+tf)/2-1]ns should be added to the parameter.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.9 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b frequency vs. ac parameter relationahip table t4312816a-6s (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 60ns 42ns 15ns 12ns 15ns 6ns 6ns 12ns 166mhz(6.0ns) 3 10 7 3 2 3 1 1 2 143mhz(7.0ns) 3 9 6 3 2 3 1 1 2 125mhz ( 8.0ns ) 2 9 6 2 2 2 1 1 2 111mhz(9.0ns) 2 7 5 2 2 2 1 1 2 100mhz ( 10.0ns ) 2 7 5 2 2 2 1 1 2 t4312816a-7s (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 63ns 42ns 15ns 14ns 15ns 7ns 7ns 14ns 143mhz(7.0ns) 3 9 6 3 2 3 1 1 2 125mhz(8.0ns) 3 9 6 2 2 2 1 1 2 111mhz ( 9.0ns ) 2 8 5 2 2 2 1 1 2 100mhz(10.0ns) 2 7 5 2 2 2 1 1 2 83mhz ( 12.0ns ) 2 6 4 2 2 2 1 1 2 t4312816a-7.5s (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 65ns 45ns 20ns 15ns 18ns 7.5ns 7.5ns 15ns 133mhz(7.5ns) 3 9 6 3 2 3 1 1 2 125mhz(8.0ns) 3 9 6 3 2 3 1 1 2 111mhz ( 9.0ns ) 2 8 5 3 2 2 1 1 2 100mhz(10.0ns) 2 7 5 2 2 2 1 1 2 83mhz ( 12.0ns ) 2 6 4 2 2 2 1 1 2 t4312816a-8s (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 68ns 48ns 20ns 16ns 20ns 8ns 8ns 16ns 125mhz(8.0ns) 3 9 6 3 2 3 1 1 2 111mhz(9.0ns) 3 9 6 3 2 3 1 1 2 100mhz ( 10.0ns ) 2 7 5 2 2 2 1 1 2 83mhz(12.0ns) 2 6 4 2 2 2 1 1 2 75mhz ( 13.0ns ) 2 6 4 2 2 2 1 1 2 t4312816a-10s (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 70ns 50ns 20ns 20ns 20ns 10ns 10ns 20ns 100mhz(10.0ns) 2 7 5 2 2 2 1 1 2 83mhz(12.0ns) 2 7 5 2 2 2 1 1 2 75mhz ( 13.0ns ) 2 6 4 2 2 2 1 1 2 66mhz(15.0ns) 2 6 4 2 2 2 1 1 2 60mhz ( 16.7ns ) 2 5 3 2 2 2 1 1 note 1 note : 1. t rdl 16.7ns is recommended for t4312816a 2. clock count formula : clock period clock value base (round off whole number).
te ch tm preliminary t4312816a tm technology inc. reserves the right p.10 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b mode register 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 jedec standard test set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0 x x 1 0 0 ltmode wt bl burst read and single write (for write through cache) 11 10 9 8 7 6 5 4 3 2 1 0 1 0 use in future 11 10 9 8 7 6 5 4 3 2 1 0 x x x 1 1 v v v v v v v vender specific 11 10 9 8 7 6 5 4 3 2 1 0 v = valid 0 0 0 0 0 ltmode wt bl mode register set x = don?t care bit2-0 wt=0 wt=1 000 1 1 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r burst length 111 full page r 0 sequential wrap type 1 interleave bit6-4 cas latency 000 r 001 r 010 2 011 3 100 r 101 r 110 r latency mode 111 r remark r : reserved mode register write timing clock cke cs ras cas we a0-a11
te ch tm preliminary t4312816a tm technology inc. reserves the right p.11 publication date:apr. 2003 to change products or specifications without notice. revision: 0.b burst length and sequence (burst of two) starting address (column address a0 binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0,1 0,1 1 1,0 1,0 (burst of four) starting address (column address a1-a0 binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 (burst of eight) starting address (column address a2-a0 binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 full page burst is an extension of the above tables of sequential addressing, with the length being 512 for 8mx16 divice. power up sequence 1. apply power and start clock, attempt to maintain cke = ?h? , l(u)dqm = ?h? and the other pin are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue mode register set command to initalize the mode register. cf.) sequence of 4 & 5 is regardless of the order.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.12 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b simplified truth table command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 9 ~a 0, a11 note register mode register set h x l l l l x x 1,2 auto refresh h entry h l l l l h x x 3 l h h h refresh self refresh exit l h h x x x x x 3 bank active & row address h x l l h h x v row address auto precharge disable l read column address auto precharge enable h x l h l h x v h column address (a0~a8) 4,5 auto precharge disable l write & column address auto precharge enable h x l h l l x v h column address (a0~a8) 4,5 burst stop h x l h h l x x 6 bank selection v l precharge both banks h x l l h l x x h 4 h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dqm h x v x 7 h h x x x no operation command h x l h h h x x (v=valid , x=don?t care , h=logic high , l=logic low) notes : 1. op code : operation code. a 0 ~a 11 , ba0~ba1 : program keys.(@mrs) 2. mrs can be issued only at both banks precharge state. a new command can be issued after 2 clock cycle of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by ?auto?. auto / self refresh can be issued only at both banks precharge state. 4. ba0~ba1 : bank select address. if both ba0 and ba1 are ?low? : at read , write , row active and precharge , bank a is selected. if both ba0 is ?low? and ba1 is ?high? : at read , write , row active and precharge , bank b is selected. if both ba0 is ?high? and ba1 is ?low? : at read , write , row active and precharge , bank c is selected. if both ba0 and ba1 are ?high? : at read , write , row active and precharge , bank d is selected if a 10 /ap is ?high? : at row precharge , ba0 and ba1 ignored and all banks are selected. 5. during burst read or write with auto precharge , new read/write command cannotbeissued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2)
te ch tm preliminary t4312816a tm technology inc. reserves the right p.13 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b single bit read-write cycle (same page) @cas latency=3,burst length=1 clock cke cs ras cas addr ba a10/ap dq we dqm 012345678910111213141516171819 t ch t cc t cl high t ras t rc *note1 t sh t ss t rp t rcd t s h t ss t ccd *note2 *note2. 3 *note2. 3 *note2. 3 *note4 *note2 t sh t ss t ss t sh t ss t sh *note3 *note3 *note3 *note4 t rac t src t slz t oh t ss t sh t sh t ss t sh t ss row active read write read precharge row active ra ca cb cc rb bs bs bs bs bs bs rb ra qa db qc :don't care
te ch tm preliminary t4312816a tmemory technology inc. reserves the right p.14 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b *note : 1. all input expect cke & dqm can be don?t care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba0 ? ba1. ba0 ba1 active & read/write 0 0 bank a 1 0 bnak b 0 1 bank c 1 1 bnak d 3. enable and disable auto precharge function are controlled by a 10 /ap in read/wirte command. a10 auto-precharge 0 disable (end of burst) 1 enable (end of burst) ba0 ba1 operation 0 0 enable read/write command for bank a . 1 0 enable read/write command for bank b . 0 1 enable read/write command for bank c . 1 1 enable read/write command for bank d . 4. a 10 /ap and ba control bank precharge when precharge command is asserted. a 10 /ap ba0 ba1 precharge 0 0 0 bank a 0 1 0 bank b 0 0 1 bank c 0 1 1 bank d 1 x x all bamks
te ch tm preliminary t4312816a tm technology inc. reserves the right p.15 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b power up sequence clock ck e cs ra s ca s addr ba a10/ap d q w e d q m 012345678910111213141516171819 t ccd high level is necessary t rp t rc t rc key raa key key raa high level is necessary high-z ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss precharge a ll b anks auto refresh auto refresh m ode register set (a-bank) row a ctive :don't care
te ch tm preliminary t4312816a tm technology inc. reserves the right p.16 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b read & write cycle at same bank @burst length = 4 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t rc d q m d q :d on't care *note1 t rcd *note2 *note4 *note3 *note3 *note4 ra ca0 rb cb0 rb ra qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db0 db1 db1 db2 db2 db3 db3 t rac t sac t oh t oh t sac t shz t shz t rdl t rdl row a ctive (a - bank) r ead (a - bank) precharg e (a - bank) row active (a -b nak) w rite (a - bnak) precharge (a-b nak) *note : 1. minimum row cycle times is requiqed to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency-1] number of valid output data is available after row precharge. last valid output will be hi-z( t shz ) after the clock. 3. access time from row active command. t cc *( t rcd +cas latency-1)+ t sac 4. output will be hi-z after the end of burst.(1,2,4,8 bit burst) burst can?t end in full page mode.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.17 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b page read & write cycle at same bank @ burst length = 4 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t ccd d q m d q :d on't care row active (a -b nak) r ead (a - bnak) r ead (a - bnak) w rite (a - bnak) w rite (a - bnak) precharge (a -b nak) *note1 *note3 *note2 t rcd t rdl t cdl ra ca0 cb0 cc0 cd0 qa0 qa1 qa0 qa1 qb0 qb0 qb1 qb2 qb1 dc0 dc1 dc0 dc1 dd0 dd1 dd0 dd2 *note : 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.18 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b page read cycle at different bank @ burst length = 4 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high d q m d q :d on't care *note1 *note2 raa caa rbb cbb cac cbd cae raa rbb qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 qbb0 qbb0 qbb1 qbb2 qbb3 qbb1 qbb2 qbb3 qac0 qac1 qac0 qac1 qbd0 qbd0 qbd1 qbd1 qae0 qae0 qae1 qae1 row active (a -b ank) r ead (a - bank) row active (b -b ank) r ead (b - bank) r ead (a - bank) r ead (b - bank) r ead (a - bank) precharge (a -b ank) *note : 1. cs can be don?t cared when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.19 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b page write cycle at different bank @ burst length = 4 clock c k e c s r a s c a s addr b a a10/ap d q w e dqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high :don't care row active (a -b ank) write (a- bank) row active (b -b ank) write (b- bank) write (a- bank) write (b- bank) precharge (a -b ank) *note1 *note2 t cdl t rdl raa caa rbb cbb cac cbd raa rbb daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 dbd1 *note : 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.20 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b read & write cycle at different bank @ burst length = 4 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high d q m d q :d on't care qaa0 raa caa rbb cbb rac cac raa rbb rac qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 dbb0 dbb1 dbb2 dbb3 dbb0 dbb1 dbb2 dbb3 qac0 qac0 qac1 qac2 qac1 *note1 t cdl row active (a -b ank) r ead (a - bank) row active (b -b ank) precharge (a -b ank) w rite (b - bank) row active (a -b ank) r ead (a - bank) *note : 1. t cdl should be met to complete write.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.21 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b read & write cycle with auto precharge @ burst length = 4 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high d q m d q :d on't care row active (a -b ank) row active (b -b ank) r ead w ith a u to precharge (a - bank) cl=2 auto precharge start p o in t (a -b an k ) cl=3 auto precharge start p o in t (a -b an k ) w rite w ith a u to precharge (b - bank) auto precharge s tart p o in t (a - bank) ra rb ca cb ra rb qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db0 db1 db1 db2 db2 db3 db3 *note : 1. t cdl should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length = 1 & 2 and brsw mode)
te ch tm preliminary t4312816a tm technology inc. reserves the right p.22 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b clock suspension & dqm operation cycle @ cas latency = 2 ,burst length = 4 clock c k e c s r a s c a s addr b a a10/ap d q w e dqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 :don't care row active read clock suspension read read qdm write write qdm clock suspension write qdm *note3 ra ca cb cc ra qa0 qa1 qa2 qa3 qb0 qb1 dc0 dc2 t shz t shz *note 1. dqm is needed to prevent bus contention.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.23 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b read interrupted by precharge command & read burst stop cycle @ burst length=full page clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high d q m d q :d on't care raa caa cab raa qaa0 qaa1 qaa2 qaa3 qaa4 qaa0 qaa1 qaa2 qaa3 qaa4 qab0 qab0 qab1 qab1 qab2 qab3 qab2 qab4 qab3 qab5 qab4 qab5 *note2 1 2 2 1 row active (a -b ank) r ead (a - bank) r ead (a - bank) burst stop precharge (a -b ank) *note : 1. burst can?t end in full page mode, so auto precharge can?t issue. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the lable 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycle?. 3. burst stop is valid at every burst length.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.24 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b write interrupted by prechareg command & write burst stop cycle @ burst length=full page clock c k e c s r a s c a s addr b a a10/ap d q w e dqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high :don't care row active (a -b ank) write (a- bank) burst stop write (a- bank) precharge (a -b ank) raa caa cab raa daa0 daa1 daa2 daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 *note3 t bdl t rdl *note : 1. burst can?t end in full page mode, so auto precharge can?t issue. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.25 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b burst read single bit write cycle @ burst length = 2 clock c k e c s r a s c a s addr b a a10/ap c l = 2 c l = 3 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high d q m d q :d on't care *note2 raa caa rbb cab rac cbc cad raa rbb rac daa0 daa0 dab0 dab0 dab1 dab1 dbc0 dbc0 dad0 dad1 dad0 dad1 row active (a -b ank) w rite (a - bank) row active (a -b ank) r ead w ith a uto precharge (a - bank) row active (a -b ank) w rite w ith a uto precharge (a - bank) r ead (a - bank) precharge (a -b ank) *note : 1. brsw modes is enabled by setting a 9 ?high? at mrs (mode register set). at the brsw mode, the burst length at write is fixed to ?1? regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the next cycle of burst-end, so in the case of brsw write command, the precharge command will be issued after two clock cycle.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.26 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b active/ precharge power down mode @ cas latency = 2, butsr length = 4 clock ck e cs ra s ca s addr ba a10/ap d q w e d q m 0 1 2 3 4 5 6 7 8 9 10111213141516171819 :d on't care precharge power- down entry precharge power- down exit row active a ctive power- down entry active power- down exit read precharge qa0 qa1 qa2 ra ca ra t shz ss tss tss tss *note1 *note3 *note2 ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss *note : 1. both banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk+ t ss prior to row active command. 3. can not violate minimum refresh specification.(64ms)
te ch tm preliminary t4312816a tm technology inc. reserves the right p.27 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b self refresh entry & exit cycle clock cke c s ras cas addr b a a 10/a p d q w e dqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 :d on't care ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss *n ote2 *n ote1 *n ote3 *n ote4 *n ote6 *n ote7 *n ote5 t ss t rcmin hi-z s elf r efresh e n try s elf r efresh e x it a uto r efresh hi-z *note : to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs inculding the system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum trc is required after cke going high to complete self refresh exit. 7. 2k cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.28 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b mode register set cycle auto refresh cycle clock c k e c s r a s c a s addr d q w e dqm 0123456 012345678910 :don't care ss ss ss ss ss ss ss ss ss ss ss ss ss ss *note2 *note1 *note3 t rpc auto refresh new command mrs new command hi-z key key hi-z high high *both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle *note : 1. cs , ras , cas & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table.
te ch tm preliminary t4312816a tm technology inc. reserves the right p.29 publication date: apr. 2003 to change products or specifications without notice. revision: 0.b package dimensions 54 lead tsop-ii (400 mil) d 28 54 1 27 e1 e a a2 b a1 c b1 dimension in mm dimension in inch symbol min nom max min nom max a - - 1.2 - - 0.047 a1 0.4 0.5 0.6 0.016 0.020 0.024 a2 - 0.15 - 0.006 b 0.24 0.32 0.40 0.009 0.012 0.016 b1 - 0.8 - 0.0315 c 0.05 0.10 0.15 0.002 0.004 0.006 d 22.12 22.22 22.62 0.871 0.875 0.905 e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.06 10.16 10.26 0.396 0.400 0.404 0 - 8 0 - 8

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